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HTG2150 8-bit 320 pixel lcd microcontroller 1 july 24, 2000 features operating voltage: 2.2v~3.6v 16k 16 bits program rom 192 8 bits data ram 8~12 bidirectional i/o lines 8 common 33~40 segment lcd driver one 16-bit programmable timer with overflow interrupts one 8-bit programmable timer with 8 stage prescaler for pfd one 8-bit programmable timer with 8 stage prescaler for time base one 8-bit pwm audio output to directly drive speaker and buzzer watchdog timer on-chip rc oscillator for system clock and 32768hz crystal oscillator for timebase and lcd driver halt function and wake-up feature reduce power consumption 8-level subroutine nesting bit manipulation instructions 63 powerful instructions one interrupt input general description the HTG2150 is an 8-bit high performance risc-like microcontroller. the single cycle in - struction and two-stage pipeline architecture make it suitable for high speed application. the device is ideally suited for multiple lcd low power application among which are calcula - tors, clock timer, game, scales, toys and hand held lcd products, as well as for battery sys - tems. preliminary
block diagram HTG2150 2 july 24, 2000 preliminary

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pad coordinates unit: m pad no. x y pad no. x y 1 880.45 1114.46 32 882.36 639.47 2 887.11 872.13 33 882.36 532.87 3 887.11 765.63 34 882.36 426.37 4 887.11 659.03 35 882.36 319.77 5 887.11 552.53 36 882.36 213.27 6 887.11 445.93 37 882.36 106.67 7 887.11 339.43 38 882.36 0.17 8 887.11 232.83 39 882.36 106.43 9 822.70 103.48 40 882.36 212.93 10 822.70 13.52 41 882.36 319.53 11 822.70 127.52 42 882.36 426.03 12 822.70 244.52 43 882.36 532.63 13 824.04 354.49 44 882.36 639.13 14 824.04 462.62 45 882.36 745.73 15 823.97 580.52 46 882.36 852.23 16 871.13 1052.80 47 824.35 1114.46 17 720.90 1052.80 48 717.85 1114.46 18 539.25 1052.80 49 611.25 1114.46 19 404.50 1051.65 50 504.75 1114.46 20 273.79 1032.67 51 398.15 1114.46 21 99.06 1097.34 52 291.65 1114.46 22 58.61 1057.70 53 185.05 1114.46 23 175.41 1057.70 54 78.55 1114.46 24 289.41 1057.70 55 28.05 1114.46 25 406.21 1057.70 56 134.55 1114.46 26 520.21 1057.70 57 241.15 1114.46 27 637.01 1057.70 58 347.65 1114.46 28 751.01 1057.70 59 454.25 1114.46 29 867.81 1057.70 60 560.75 1114.46 30 882.36 852.57 61 667.35 1114.46 31 882.36 745.97 62 773.85 1114.46 pad description pad no. pad name i/o mask option description 38~62 1~8 seg0~seg24 seg25~seg32 o lcd segment signal output. 9~12 pb4~pb7/ seg33~seg36 i/o or o input/output or segment output selectable as bidirectional input/output or lcd segment signal output by mask option. on bidirectional input/output port. software instruc - tions determine the cmos output or schmitt trig - ger input with pull-high resistor. pb4~pb7 share pad with seg33~seg36. HTG2150 4 july 24, 2000 preliminary
pad no. pad name i/o mask option description 13 int /seg37 i or o interrupt input or segment 37 output selectable as external interrupt schmitt trigger input or lcd segment 37 signal output by mask option. external interrupt schmitt trigger input with pull-high resistor. edge triggered activated on a high to low transition. int shares pad with seg37. 15 14 xin/seg39 xout/seg38 ioro o crystal or segment output selectable as 32768hz crystal oscillator or lcd segment signal output by mask option. crystal oscillator (32.768khz) for timer 3 and lcd clock. xin shares pad with seg39; xout shares pad with seg38. 16 res i schmitt trigger reset input. active low without pull-high resistor. 17 pwm1 o cmos positive pwm cmos output 18 pwm2 o cmos negative pwm cmos output 19 vdd positive power supply 20 osci i osci is connected to the rc network of the in - ternal system clock. 21 vss negative power supply, ground 22~29 pa0~pa7 i/o wake-up or none wake-up bidirectional 8-bit input/output port. each bit can be configured as a wake-up input by mask option. software instructions determine the cmos output or schmitt trigger input with pull-high resistor. 37~31 com7~com0 o lcd common signal output absolute maximum ratings supply voltage.............................. 0.3v to 3.6v storage temperature................. 50 cto125 c input voltage .................v ss 0.3v to v dd +0.3v operating temperature ..................0 cto70 c note: these are stress ratings only. stresses exceeding the range specified under absolute maxi - mum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged expo - sure to extreme conditions may affect device reliability. HTG2150 5 july 24, 2000 preliminary
d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 2.2 3.6 v i dd operating current (rc osc) 3v no load, f sys =4mhz 12ma i stb1 standby current with 7 a lcd bias option (rtc on, lcd on) 3v no load, halt mode 20 a i stb2 standby current lcd bias off option (rtc on, lcd off) 3v no load, halt mode 5 a v il1 input low voltage for pa/pb 3v 0 0.9 v v ih1 input high voltage for pa/pb 3v 2.1 3v v il2 input low voltage (int )3v 0 0.7 v v ih2 input high voltage (int )3v 2.3 3v v il3 input low voltage (res )3v 1.5 v v ih3 input high voltage (res )3v 2.4 v i oh1 port a, port b source current 3v v oh =2.7v 1 2 ma i oh2 segment, common output source current 3v v oh =2.7v 50 90 a i oh3 pwm1/pwm2 source current 3v v oh =2.7v 8 10 ma i ol1 port a, port b sink current 3v v ol =0.3v 1.5 4 ma i ol2 segment, common output sink current 3v v ol =0.3v 80 130 a i ol3 pwm1/pwm2 sink current 3v v oh =0.3v 12 16 ma r ph pull-high resistance of pa/pb and int 3v 40 60 80 k a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys system clock (rc osc) 3v 400 4000 khz 2.4v 400 2000 2.2v 400 1000 t res external reset low pulse width 1 s t sst system start-up timer period power-up or wake-up from halt 1024 t sys t int interrupt pulse width 1 s note: t sys =1/f sys HTG2150 6 july 24, 2000 preliminary
HTG2150 7 july 24, 2000 preliminary " . + " . + " . + 2 & * *; = >* *; :"= 2 & * *; ? " = >* *; = 2 & * *; ? . = >**; ?"= ?" ?. $ 7@ 8 @! 8 @" 4"9. ", 8 @ *8 @* *8 /* *# # "*-*%& %&*** >*'*a ** 77* ",( * * *# *# & "*- !!!!5 "2225 .!!!5 2225 execution flow functional description execution flow the system clock for the HTG2150 is derived from an rc oscillator. the system clock is inter - nally divided into four non-overlapping clocks. one instruction cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while decoding and execution takes the next in - struction cycle. however, the pipelining scheme causes each instruction to effectively execute in one cycle. if an instruction changes the program coun - ter, two cycles are required to complete the instruc - tion. program counter pc the 13-bit program counter (pc) controls the sequence in which the instructions stored in the program rom are executed and its contents specify a maximum of 8192 addresses. after accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip execution, loading pcl register, subrou- tine call, initial reset, internal interrupt, exter- nal interrupt or return from subroutine, the pc manipulates the program transfer by loading the address corresponding to each instruction. the conditional skip is activated by instruction. once the condition is met, the next instruction, fetched during the current instruction execu - tion, is discarded and a dummy cycle replaces it to get the proper instruction. otherwise pro - ceed with the next instruction. the lower byte of the program counter (pcl) is a readable and writeable register (06h). moving data into the pcl performs a short jump. the destination will be within 256 loca - tions. when a control transfer takes place, an addi - tional dummy cycle is required. program memory rom the program memory, which contains execut - able program instructions, data and table infor - mation, is composed of a 16384 x 16 bit format. however as the pc (program counter) is com - prised of only 13 bits, the remaining 1 rom ad - dress bit is managed by dividing the program memory into 2 banks, each bank having a range between 0000h and 1fffh. to move from the present rom bank to a different rom bank, the higher 1 bit of the rom address are set by the bp (bank pointer), while the remaining 13 bits of the pc are set in the usual way by exe- cuting the appropriate jump or call instruction. as the full 14 address bits are latched during the execution of a call or jump instruction, the correct value of the bp must first be setup be- fore a jump or call is executed. when either a software or hardware interrupt is received, note that no matter which rom bank the pro-
HTG2150 8 july 24, 2000 preliminary mode program rom address *13 *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 initial reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 external interrupt 0 0 0 0 0 0 0 0 0 0 0 1 0 0 timer counter 0 overflow 0 0 0 0 0 0 0 0 0 0 1 0 0 0 timer 2 overflow 0 0 0 0 0 0 0 0 0 1 0 0 0 0 timer 3 overflow 0 0 0 0 0 0 0 0 0 1 0 1 0 0 d/a buffer empty interrupt 0 0 0 0 0 0 0 0 0 1 1 0 0 0 skip pc+2 loading pcl *13 *12 *11 *10 *9 *8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch bp.5 #12 #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s13 s12 s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 program rom address note: *13~*0: program rom address @7~@0: pcl bits #12~#0: instruction code bits s13~s0: stack register bits bp.5: bit 5 of bank pointer (04h) gram is in the program will always jump to the appropriate interrupt service address in bank 0. the original full 14 bit address will be stored on the stack and restored when the relevant ret/reti instruction is executed, automati - cally returning the program to the original rom bank. this eliminates the need for pro - grammers to manage the bp when interrupts occur. certain locations in bank 0 of program memory are reserved for special usage: rom bank 0 (bp5~bp7=000b) the rom bank 0 ranges from 0000h to 1fffh. location 000h this area is reserved for the initialization program. after chip reset, the program al - ways begins execution at location 000h. location 004h this area is reserved for the external inter - rupt service program. if the int input pin is activated, and the interrupt is enabled and the stack is not full, the program begins exe - cution at location 004h. location 008h this area is reserved for the timer counter 0 in - terrupt service program. if a timer interrupt re - sults from a timer counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008h. !!!!5 !!!+5 !!!45 1*76* >7* *- **!* *- ",*- 2225 !!! 5 *.* *- ** *- !"!5 !"+5 # *-''* $* !"45 program memory
HTG2150 9 july 24, 2000 preliminary instruction(s) table location *13 *12 *11 *10 *9 *8 *7 *6 *5 *4 *3 *2 *1 *0 tabrdc [m] #5 #4 #3 #2 #1 #0 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1 1 1 1 1 1 @7 @6 @5 @4 @3 @2 @1 @0 table location note: @7~@0: tblp register bit 7~bit 0 #5~#0: tbhp register bit 13~bit 8 *13~*0: current program rom table address bit 13~bit 0 location 010h/014h this area is reserved for the timer 2/3 interrupt service program. if a timer interrupt results from a timer 2/3 overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 010h/014h. location 018h this area is reserved for the d/a buffer empty interrupt service program. after the system latch a d/a code at ram address 28h, the in - terrupt is enable, and the stack is not full, the program begins execution at location 020h. location 020h for best condition, this is the starting loca - tion for writing the program.. rom bank 1 (bp5~bp7=001b) the range of the rom starts from 2000h to 3fffh. table location any location in the rom space can be used as look up tables. the instructions tabrdc [m] (use for any bank) and tabrdl [m] (only used for last page of program rom) transfers the contents of the lower-order byte to the specified data memory, and the higher-order byte to tblh (08h). only the destination of the lower-order byte in the table is well-defined. the higher-order byte of the ta- ble word are transferred to the tblh. the ta- ble higher-order byte register (tblh) is read only. the table pointer (tbhp, tblp) is a read/write register (1fh, 07h), which indi- cates the table location. before accessing the table, the location must be placed in tblp. the tblh is read only and cannot be re- stored. if the main routine and the isr (inter - rupt service routine) both employ the table read instruction, the contents of the tblh in the main routine are likely to be changed by the table read instruction used in the isr. er - rors can occur. in other words, using the table read instruction in the main routine and the isr simultaneously should be avoided. how - ever, if the table read instruction has to be ap - plied in both the main routine and the isr, the interrupt is supposed to be disabled prior to the table read instruction. it will not be en - abled until the tblh has been backed up. all table related instructions need two cycles to complete the operation. these areas may function as normal program memory depend - ing upon the requirements. stack register stack this is a special part of the memory which is used to save the contents of the program coun - ter (pc) only. the stack is organized into eight levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer (sp) and is neither readable nor writeable. at a subroutine call or interrupt ac - knowledgment, the contents of the program counter and rom address a13 bit latch data are pushed onto the stack. at the end of a sub- routine or an interrupt routine, signaled by a return instruction (ret or reti), the program counter and rom address a13 bit latch data are restored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. if the stack is full and a non-masked interrupt takes place, the interrupt request flag will be re- corded but the acknowledgment will be inhibited. when the stack pointer is decremented (by ret or reti), the interrupt will be serviced. this fea - ture prevents stack overflow allowing the pro -
HTG2150 10 july 24, 2000 preliminary grammer to use the structure more easily. in a similar case, if the stack is full and a call is subsequently executed, stack overflow occurs and the first entry will be lost (only the most recent eight return address are stored). data memory ram bank 0 (bp4~bp0=00000) the bank 0 data memory includes special purpose and general purpose memory. the special purpose memory is addressed from 00h to 2fh, while general purpose memory is addressed from 40h to ffh. all data memory areas can handle arithmetic, logic, increment, decrement and rotate operations directly. ex - cept for some dedicated bits, each bit in the data memory can be set and reset by the set [m].i and clr [m].i instructions, respectively. they are also indirectly accessible through the memory pointer registers (mp0;01h, mp1;03h). bank 15 (bp4~bp0=01111b) the range of ram starts from 80h to a7h. on the lcd, every bit stands for one dot. if the bit is 1 , the light of the dot on the lcd will be turned on. if the bit is 0 , then it will be turned off. only mp1 can deal with the memory of this range. the contrast form of ram location, com - mon, and segment is as follows. indirect addressing register location 00h and 02h are indirect addressing registers that are not physically implemented. any read/write operation of [00h] and [02h] ac- cess data memory are pointed to by mp0 (01h) and mp1 (03h) respectively. reading location 00h or 02h indirectly will return the result 00h. writing indirectly results in no operation. the function of data movement between two indi- rect addressing registers, is not supported. the memory pointer registers, mp0 and mp1, are 8-bit registers which can be used to access the data memory by combining corresponding indi - rect addressing registers but bank 15 can use mp1 only. accumulator the accumulator is closely related to alu oper - ations. it is also mapped to location 05h of the data memory and it can carry out immediate data operations. the data movement between two data memories has to pass through the ac - cumulator. 25 225 . . 5 85 3 3 b#% +!5 " 5 " 5 "25 .!5 ."5 ..5 .5 .+5 ./5 .,5 .5 .45 .95 .# 5 .8 5 . 5 . 5 . 5 .25 !5 % % * 7* * *# * **c!!c 8 *-*."!* d! e* 4!5 #5 8 @*"/* * $ ;+!*8 $=
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HTG2150 11 july 24, 2000 preliminary lcd driver output the maximum output number of the HTG2150 lcd driver is 8 40. the lcd driver bias type is r type, no external capacitor is required and the bias voltage is 1/4 bias. some of the segment out - puts share pins with another pins, pb4~pb7 (seg33~seg36), int (seg37), xout (seg38), xin (seg39). whether segment output or i/o pin can individually be decided by mask option. lcd driver output can be enabled or disabled by setting the lcd (bit 6 of lcdc; 2eh) without the influence of the related memory condition. there is a special function for lcd display, which is ro - tate function. there are 8 kinds of rotate func - tion, (user can change the data of the ss0 to ss3.) an example of an lcd driving waveform (1/8 duty, 1/4 bias) is shown below. " . + / , 4 /".5 6 ! +* .+* "+*
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HTG2150 12 july 24, 2000 preliminary rotate description ssl3 ssl2 ssl1 ssl0 x000 the pad of common 0 is connected to common 0 and the pad of common 1 is connected to common 1 and so on. x001 the pad of common 0 is connected to common 1 and the pad of common 1 is connected to common 2 and so on. x010 the pad of common 0 is connected to common 2 and the pad of common 1 is connected to common 3 and so on. x011 the pad of common 0 is connected to common 3 and the pad of common 1 is connected to common 4 and so on. x100 the pad of common 0 is connected to common 4 and the pad of common 1 is connected to common 5 and so on. x101 the pad of common 0 is connected to common 5 and the pad of common 1 is connected to common 6 and so on. x110 the pad of common 0 is connected to common 6 and the pad of common 1 is connected to common 7 and so on. x111 the pad of common 0 is connected to common 7 and the pad of common 1 is connected to common 0 and so on. 2fh register register bit no. label function lcdc 0~5 can r/w (default 000000b) 6 lcd control the lcd output (0=disable; 1=enabled) (default=1) 7rc lcd clock source select (default=0) 1= 32768hz crystal 0= system clock lcdc register
HTG2150 13 july 24, 2000 preliminary arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic operation. the alu provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of a data op - eration but also changes the status register. status register status this 8-bit register (0ah) contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pd) and watchdog time-out flag (to). it also records the status information and controls the operation se - quence. with the exception of the to and pd flags, bits in the status register can be altered by instruc - tions like any other register. any data written into the status register will not change the to or pd flags. in addition it should be noted that operations related to the status register may give different results from those intended. the to and pd flags can only be changed by system power up, watchdog timer overflow, executing the halt instruction and clearing the watch - dog timer. the z, ov, ac and c flags generally reflect the status of the latest operations. in addition, on entering the interrupt sequence or executing the subroutine call, the status reg - ister will not be automatically pushed onto the stack. if the contents of status are important and if the subroutine can corrupt the status register, precautions must be taken to save it properly. interrupt the HTG2150 provides an external interrupt and a pwm d/a interrupt and internal timer inter - rupts. the interrupt control register (intc;0bh, intch;1eh) contains the interrupt control bits to set the enable/disable and the interrupt request flags. once an interrupt subroutine is serviced, all other interrupts will be blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may happen during this interval but only the inter- labels bits function c0 c is set if the operation results in a carry during an addition operation or if a bor- row does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. ac 1 ac is set if the operation results in a carry out of the low nibbles in addition or no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. z2 z is set if the result of an arithmetic or logic operation is zero; otherwise z is cleared. ov 3 ov is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. pd 4 pd is cleared when either a system powers up or a clr wdt instruction is exe - cuted. pd is set by executing the halt instruction. to 5 to is cleared by a system power-up or executing the clr wdt or halt in - struction. to is set by a wdt time-out. 6, 7 undefined bits, read as 0 . status register
HTG2150 14 july 24, 2000 preliminary rupt request flag is recorded. if a certain inter - rupt needs servicing within the service routine, the programmer may set the emi bit and the corresponding bit of the intc to allow interrupt nesting. if the stack is full, the interrupt request will not be acknowledged, even if the related in - terrupt is enabled, until the sp is decremented. if immediate service is desired, the stack must be prevented from becoming full. all these kinds of interrupt have a wake-up ca - pability. as an interrupt is serviced, a control transfer occurs by pushing the program counter and a13 bit onto the stack followed by a branch to subroutines at specified locations in the pro - gram memory. only the program counter and a13 bit are pushed onto the stack. if the con - tents of the register and status register (status) are altered by the interrupt service program which corrupt the desired control se - quence, the contents should be saved first. external interrupt is triggered by a high to low transition of int and the related interrupt re - quest flag (eif; bit 4 of intc) will be set. when the interrupt is enabled, and the stack is not full and the external interrupt is active, a sub - routine call to location 04h will occur. the in- terrupt request flag (eif) and emi bits will be cleared to disable other interrupts. the internal timer counter 0 interrupt is ini- tialized by setting the timer counter 0 interrupt request flag (t0f; bit 5 of intc), resulting from a timer 0 overflow. when the interrupt is en - abled, and the stack is not full and the t0f bit is set, a subroutine call to location 08h will oc - cur. the related interrupt request flag (t0f) will be reset and the emi bit cleared to disable further interrupts. the timer 2/3 interrupts are operated in the same manner as timer 0. while et2i/et3i and t2f/t3f are the related control bits and the re - lated request flags of tmr2/tmr3, which lo - cate at bit0/bit1 and bit4/bi5 of the intch respectively. during the execution of an interrupt subroutine, other interrupt acknowledgments are held until the reti instruction is executed or the emi bit and the related interrupt control bit are set t o1(if the stack is not full). to return from the interrupt subroutine, the ret or reti instruction may be invoked. reti will set the emi bit to enable an in - terrupt service, but ret will not. interrupts occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding interrupts are en - abled. in the case of simultaneous requests the priorities applied are shown in the following ta- ble. these can be masked by resetting the emi bit. register bit no. label function intc 0 emi controls the (global) interrupt (1=enable; 0=disable) 1 eei controls the external interrupt (1=enable; 0=disable) 2 et0i controls the timer counter 0 interrupt (1=enable; 0=disable) 3 unused bit 4 eif external interrupt request flag (1=active; 0=inactive) 5 t0f internal timer counter 0 request flag (1=active; 0=inactive) 6, 7 unused bit intc register
HTG2150 15 july 24, 2000 preliminary register bit no. label function intch 0 et2i controls the timer 2 interrupt (1=enable; 0=disable) 1 et3i controls the timer 3 interrupt (1=enable; 0=disable) 2 pwmi pwm d/a interrupt (1=enable; 0=disable) 3 should be set as 0 always 4 t2f internal timer 2 request flag (1=active; 0=inactive) 5 t3f internal timer 3 request flag (1=active; 0=inactive) 6 pwmf pwm d/a flag (1=active; 0=inactive) 7 should be set as 0 always intch register no. interrupt source priority vector a external interrupt 1 04h b timer counter 0 overflow 2 08h d timer 2 overflow 4 10h e timer 3 overflow 5 14h f pwm d/a interrupt 6 18h the timer counter 0 and timer 2/3 interrupt re- quest flag (t0f/t2f/t3f), external interrupt re- quest flag (eif), pwm d/a interrupt request flag (pwmf),enable timer 0/2/3 bit (et0i/et2i/et3i) , enable pwm d/a interrupt (pwmi), enable ex- ternal interrupt bit (eei) and enable master in- terrupt bit (emi) constitute an interrupt control register (intc/intch) which is located at 0bh/1eh in the data memory. emi, eei, et0i, et2i, et3i, pwmi are used to control the en - abling/disabling of interrupts. these bits prevent the requested interrupt from being serviced. once the interrupt request flags (t0f, t2f, t3f, eif, pwmf) are set, they will remain in the intc/intch register until the interrupts are ser - viced or cleared by a software instruction. it is recommended that a program does not use the call subroutine within the interrupt subroutine. interrupts often occur in an unpre - dictable manner or need to be serviced immedi - ately in some applications. if only one stack is left and enabling the interrupt is not well con trolled, the call subroutine should not operate in the in - terrupt subroutine as it will damage the original control sequence. oscillator configuration there are two oscillator circuits in the HTG2150. the rc oscillator signal provides the internal system clock. the halt mode stops the system oscillator and ignores any external signal to conserve power. only the rc oscillator is de - signed to drive the internal system clock. the rtc oscillator provides the timer 3 and lcd driver clock source. the rc oscillator needs an external resistor connected between osci and vss. the resis - tance value must range from 50k to 400k . however, the frequency of the oscillation may vary with v dd , temperature and the chip itself due to process variations. it is, therefore, not suit - able for timing sensitive operations where accu - rate oscillator frequency is desired. * 77 .,45 6 * 77 system and rtc oscillator
HTG2150 16 july 24, 2000 preliminary 4:-* 3 * 7 :-* 4::"* 3 * : 3!03. 3 watchdog timer there is another oscillator circuit designed for the real time clock. in this case, only the 32768hz crystal can be applied. the crystal should be connected between xin and xout, and two external capacitors are required for the oscillator circuit in order to get a stable fre - quency. the rtc oscillator is used to provide clock source for the lcd driver and timer 3. it can be enabled or disabled by mask option. the wdt oscillator is a free running on-chip rc oscillator, requiring no external compo - nents. even if the system enters the power down mode, and the system clock is stopped, the wdt oscillator still runs with a period of approximately 78 s. the wdt oscillator can be disabled by mask option to conserve power. watchdog timer wdt the wdt clock source is implemented by a dedi - cated rc oscillator (wdt oscillator). this timer is designed to prevent a software malfunction or sequence jumping to an unknown location with unpredictable results. the watchdog timer can be disabled by mask option. if the watchdog timer is disabled, all the executions related to wdt result in no operation. when the internal wdt oscillator (rc oscilla- tor with 83 s period normally) is enable, it is first divided by 256 (8 stages) to get the nominal time-out period of approximately 21ms. this time-out period may vary with temperature, v dd and process variations. by invoking the wdt prescaler, longer time-out periods can be realized. writing data to ws2, ws1, ws0 (bits 2,1,0 of the wdts) can give different time-out periods. if ws2, ws1, ws0 are all equal to 1, the division ratio is up to 1:128, and the maxi - mum time-out period is 2.6 seconds. ws2 ws1 ws0 division ratio 000 1:1 001 1:2 010 1:4 011 1:8 1 0 0 1:16 1 0 1 1:32 1 1 0 1:64 1 1 1 1:128 wdts register the wdt overflow under normal operation will initialize chip reset and set the status bit to. whereas in the halt mode, the overflow will initialize a warm reset only the pc and sp are reset to zero. to clear the wdt contents (in - cluding the wdt prescaler), three methods are adopted; external reset (a low level to res ), software instructions, or a halt instruction. the software instruction is clr wdt , execu - tion of the clr wdt instruction will clear the wdt. power down operation halt the halt mode is initialized by the halt in- struction and results in the following... the system oscillator will turn off but the wdt oscillator keeps running (if the wdt os- cillator is selected). the contents of the on-chip ram and regis- ters remain unchanged. wdt and wdt prescaler will be cleared and do recounting again.
HTG2150 17 july 24, 2000 preliminary all i/o ports maintain their original status. the pd flag is set and the to flag is cleared. the system can leave the halt mode by means of an external reset, an interrupt, an external falling edge signal on port a or a wdt overflow. an external reset causes a device initialization and the wdt overflow performs a warm reset . by examining the to and pd flags, the reason for chip reset can be determined. the pd flag is cleared when the system powers up or upon exe - cuting the clr wdt instruction and is set when the halt instruction is executed. the to flag is set if the wdt time-out occurs, and causes a wake-up that only resets the pc and sp, the oth - ers maintain their original status. the port a wake-up and interrupt methods can be considered as a continuation of normal exe - cution. each bit in port a can be independently selected to wake up the device by mask option. awakening from an i/o port stimulus, the pro - gram will resume execution of the next instruc - tion. if awakening from an interrupt, two sequences may happen. if the related interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruction. if the interrupt is en- abled and the stack is not full, the regular inter- rupt response takes place. once a wake-up event occurs, it takes 1024 t sys (system clock period) to resume normal opera- tion. in other words, a dummy cycle period will be inserted after the wake-up. if the wake-up results from an interrupt acknowledge, the ac- tual interrupt subroutine will be delayed by one more cycle. if the wake-up results in the next instruction execution, this will be executed im- mediately after a dummy period has finished. if an interrupt request flag is set to 1 before en - tering the halt mode, the wake-up function of the related interrupt will be disabled. to minimize power consumption, all i/o pins should be carefully managed before entering the halt status. reset there are three ways in which a reset can occur: res reset during normal operation res reset during halt wdt time-out reset during normal operation the wdt time-out during halt is different from other chip reset conditions, since it can perform a warm reset that just resets the pc and sp, leaving the other circuits in their origi - nal state. some registers remain unchanged during other reset conditions. most registers are reset to the initial condition when the re - set conditions are met. by examining the pd and to flags, the program can distinguish be - tween different chip resets . to pd reset conditions 0 0 res reset during power-up uu res reset during normal operation 0 1 res wake-up halt 1u wdt time-out during normal operation 1 1 wdt wake-up halt note: u means unchanged to guarantee that the system oscillator has started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses when the system powers up or awakes from the halt state. when a system power-up occurs, the sst delay is added during the reset period. but when the reset comes from the res pin, the sst delay is disabled. any wake-up from halt will enable the sst delay.
HTG2150 18 july 24, 2000 preliminary the functional unit chip reset status are shown below. pc 000h interrupt disable prescaler clear wdt clear. after master reset, wdt begins counting timer (0/2/3) off lcd display enable pull-high of resb with input/output ports input mode sp points to the top of the stack timer 0 the timer 0 contains 16-bit programmable count-up counters and the clock source come from the system clock divided by 4. there are three registers related to timer coun - ter 0; tmr0h (0ch), tmr0l (0dh), tmr0c (0eh). writing tmr0l only writes the data into a low byte buffer, and writing tmr0h will write the data and the contents of the low byte buffer into the timer 0 preload register (16-bit) simultaneously. the timer 0 preload register is changed by writing tmr0h operations and writing tmr0l will keep the timer 0 preload register unchanged. reading tmr0h will also latch the tmr0l into the low byte buffer to avoid the false timing problem. reading tmr0l returns the contents of the low byte buffer. in other words, the low byte of timer counter 0 cannot be read directly. it must read the tmr0h first to make the low byte contents of timer 0 be latched into the buffer. the tmr0c is the timer 0 control register, which defines the timer 0 options. the timer counter control registers define the operating mode, counting enable or disable and active edge. if the timer counter starts counting, it will count from the current contents in the timer counter to ffffh. once an overflow occurs, the counter is reloaded from the timer counter preload register and generates the correspond- ing interrupt request flag (t0f; bit of intc) at the same time. to enable the counting operation, the timer on bit (ton; bit 4 of tmr0c) should be set to 1. the overflow of the timer counter is one of the wake-up sources. no matter what the operation mode is, writin ga0to et0i can disable the cor - responding interrupt service. in the case of timer counter off condition, writ - ing data to the timer counter preload register will also reload that data to the timer counter. but if the timer counter is turned on, data written to the timer counter will only be kept in the timer counter preload register. the timer counter will still operate until overflow occurs. * : & ** reset timing chart reset circuit 3 5#% 3 : 7 3 * f:* "!: 7* " reset configuration
HTG2150 19 july 24, 2000 preliminary the state of the registers is summarized in the following table: register reset (power on) wdt time-out (normal operation) res reset (normal operation) res reset (halt) wdt time-out (halt) tmr0h xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr0l xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr0c 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- tmr2 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr2c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu tmr3 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tmr3c 00-0 1000 00-0 1000 00-0 1000 00-0 1000 uu-u uuuu intch 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu tbhp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu program counter 0000h 0000h 0000h 0000h 0000h mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu status --00 xxxx --1u uuuu --uu uuuu --01 uuuu --11 uuuu bp 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu lcdc 0100 0000 0100 0000 0100 0000 0100 0000 uuuu uuuu intc 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu wdts 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 0000 1111 0000 1111 0000 1111 0000 uuuu uuuu pbc 1111 0000 1111 0000 1111 0000 1111 0000 uuuu 0000 comr 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu pwmc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pwm xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu x
talc 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu note: * means warm reset u means unchanged x means unknown
HTG2150 20 july 24, 2000 preliminary when the timer counter (reading tmr0h) is read, the clock will be blocked to avoid er - rors. as this may results in a counting error, this must be taken into consideration by the programmer. timer 2/3 timer 2 is an 8-bit counter, and its clock source comes from the system clock divided by an 8-stage prescaler. there are two registers re- lated to timer 2 ; tmr2 (21h) and tmr2c (22h). two physical registers are mapped to tmr2 location; writing tmr2 makes the start - ing value be placed in the timer 2 preload regis - ter and reading the tmr2 gets the contents of the timer 2 counter. the tmr2c is a control register, which defines the division ratio of the prescaler and counting enable or disable. writing data to b2, b1 and b0 (bits 2, 1, 0 of tmr2c) can yield various clock sources. once the timer 2 starts counting, it will count from the current contents in the counter to ffh. once an overflow occurs, the counter is reloaded from a preload register, and generates an interrupt request flag (t2f; bit 4 of intch). to enable the counting operation, the timer on bit (ton; bit 4 of tmr2c) should be set to 1 . for proper operation, bit 6 of tmr2c should be set to 1 and bit 3, bit7 should be set to 0 . the timer 2 can also be used as pfd output by setting pwm1 and pwm2 to be pfd and pfdb output respectively by 2fh.7 and 2fh.6. when the pfd/pfdb function is selected, setting 2fh.4/2fh.5 to 1 will enable the pfd/pfdb output and setting 2fh.4/2fh.5 to 0 will dis - able the pfd/pfdb output. pfd frequency: t2f/[256-tmr2) 2] timer 3 has the same structure and operating manner with timer 2, except for clock source and pfd function. the timer 3 can be used as a time base to generate a regular internal inter- rupt. the clock source of timer 3 can come from rtc osc (x
tal 32khz) or system clock di- vided by an 8-stage prescaler. if the rtc mask option is enabled, a 32khz crystal is needed across xin and xout pins. the 32khz signal is processed by an 8-stage prescaler to yield various counting clock for timer 3. there are 2 registers related to timer 3; tmr3 (24h) and tmr3c (25h). writing data to b2, b1, b0 (bit 2, 1, 0 of tmr3c) can yield various counting clock. label bits function 0~2 unused bits, read as 0 . te 3 to define the tmr0 active edge of the timer counter (0=active on low to high; 1=active on high to low) ton 4 to enable/disable timer counting (0=disabled; 1=enabled) 5 unused bits, read as x . tm0, tm1 6, 7 0, 1=internal clock tmr0c register * *! 7* *! *8 7 1'7f * %f *8 $ 8'' $ 7@+ timer counter 0
HTG2150 21 july 24, 2000 preliminary )*%(* 4: 7 *. 7* *. *8 7 1'7f .25 g+ * .' . .25 g/ 3 . .25 g 3 . 3 " .25 g, 3 "* timer 2 label bits function ssl 3~0 3~0 lcd common used pfd 4 to enable/disable pfd output (0=disable; 1=enable) pfdb 5 to enable/disable pfdb output (0=disable; 1=enable) pwm1 6 to select pfdb/pwm1 output (0=pwm1; 1=pfdb) pwm2 7 to select pfd/pwm2 output (0=pwm2; 1=pfd) 2fh register * 7 4* * 7 %*1 ;/".5 6= .( * b# % . 5 g 4* * 7 $ 7@ 2! 2" ' *.,45 6 ,+ @* timer 3
HTG2150 22 july 24, 2000 preliminary tmr2c t2f bit 2 bit 1 bit 0 0 0 0 sys clk/2 0 0 1 sys clk/4 0 1 0 sys clk/8 0 1 1 sys clk/16 1 0 0 sys clk/32 1 0 1 sys clk/64 1 1 0 sys clk/128 1 1 1 sys clk/256 tmr2c bit 4 to enable/disable timer counting (0=disable;1=enable) tmr2c bit 3 always write 0 tmr2c bit 5 always write tmr2c bit 6 always write 1 tmr2c bit 7 always write 0 f1 can select 4 frequency by mask option auto mask option f0 sys clk near 512khz sys clk/16 sys clk near 1024khz sys clk/32 sys clk near 2048khz sys clk/64 sys clk near 4096khz sys clk/128 tmr3c t3f bit 2 bit 1 bit 0 0 0 0 f1/2 0 0 1 f1/4 0 1 0 f1/8 0 1 1 f1/16 1 0 0 f1/32 1 0 1 f1/64 1 1 0 f1/128 1 1 1 f1/256 time base frequency= t3f / (256 tmr3) tmr3c bit 4 to enable/disable timer counting (0=disable; 1=enable) tmr3c bit 3 always write 0 tmr3c bit 5 always write 0 tmr3c bit 6 always write 1 tmr3c bit 7 always write 0
HTG2150 23 july 24, 2000 preliminary input/output ports there are 12 bidirectional input/output lines in the HTG2150, labeled pa and pb, which are mapped to the data memory of [12h], [14h], re - spectively. all these i/o ports can be used for in - put and output operations. for input operation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruc - tion mov a,[m] (m=12h, 14h). for output op - eration, all data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pbc) to control the input/output configuration. with this control register, cmos output or schmitt trigger input with or without pull-high resistor (mask option) structures can be recon - figured dynamically under software control. to function as an input, the corresponding latch of the control register must write 1 . the pull-high resistance will exhibit automatically if the pull-high option is selected. the input source also depends on the control register. if the control register bit is 1 , the input will read the pad state. if the control register bit is 0 , the contents of the latches will move to the in - ternal bus. the latter is possible in read-modify-write instruction. for output function, cmos is the only configuration. these control registers are mapped to locations 13h, 15h. after a chip reset, these input/output lines stay at high levels or floating (mask option). each bit of these input/output latches can be set or cleared by the set [m].i or clr [m].i (m=12h, 14h) instruction. some instructions first input data and then fol - low the output operations. for example, the set [m].i, clr [m].i, cpl [m] and cpla [m] instructions read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. each line of port a has the capability to wake-up the device. port b are share pad, each pin func - tion are defined by mask option, the pb7 shares with seg36. the pb6, pb5 and pb4 share with seg35, seg34 and seg33. if the segment out - put is selected, the related i/o register (pb) can - not be used as general purpose register. reading the register will result to an unknown state. pwm interface the HTG2150 provides an 8 bit (bit 7 is a sign bit) pwm d/a interface, which is good for speech synthesis. the user can record or syn - thesize the sound and digitize it into the pro- gram rom. these sound could be played back in sequence of the functions as designed by the internal program rom. there are several algo- rithms that can be used in the HTG2150, they are ... pcm, law, dpcm, adpcm..... . h ( h ( h ##*8 3 * 7* & * * 7* 3 * * $ *3 @: *; # *7$= 3 #( 77: #!0 # 8+0 8 @ * @ * h input/output ports
HTG2150 24 july 24, 2000 preliminary the pwm circuit provides two pad outputs: pwm2, pwm1 which can directly drive a piezo ora32 speaker without adding any external element. refer to the application circuits. the pwm clock source comes from the system clock divided by a 3-bit prescaler. setting data to p0, p1 and p2 (bit 3, 4, 5 of 27h) can yield various clock sources. the clock source are use for pwm modulating clock and sampling clock. after setting the start bit (bit 0 27h) and the next falling edge coming from the prescaler, the div will generate a serial clock to pwm coun - ter for modulating and pwmi for interrupt. the pwm counter latch data at the first f1 clock falling edge and the start counter at f1 rising edge. the f2 clock is synchronous with the first f1 clock and it is also connected to the pwm output latch. in setting the start bit initial status, the pwm1 dac outputs a high level and change the output status to low while the 7 bits counter overflows. bz/sp 6/7 bit f1 f2 (sampling rate device 0 0 f0 f0/64 32 speaker 0 1 f0 f0/128 32 speaker 1 0 f0 f0/64 buzzer/8 speaker 1 1 f0 f0/128 buzzer/8 speaker note: f1: for pwm modulation clock and f2 for sampling clock. f0: system /[n+1] n=0~7 (n:3 bits preload counter) on the above table, we can easily see that the sampling rate is dependent on the system clock. if start bit is set to 0 , the pwm2 and pwm1 will output a gnd level voltage. label bits function d/a 0 d/a control. 0:start ; 1:stop bz/sp 1 output driver select 1:buzzer ; 0:speaker bit 2 pwm counter bit select 1:7 bits ; 0:6 bits p0~p2 3~5 3 bits preload counter, bit 5/4/3:000b~111b (0~7) bit 3:lsb d0, d1 6, 7 pwmi d0 d1 samping time/pwm interrupt 00 1 01 2 10 4 11 8 pwm control register bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 7 bit d0 d1 d2 d3 d4 d5 d6 d7 6 bit x d1d2d3d4d5d6d7 note: x means don
t care. bit7: sign bit pwm data buffer 2! *- 2" 2. * 7* ".4*7@ %& 7 bits pwm counter bit
HTG2150 25 july 24, 2000 preliminary $ *7@ 7 3 * 8''*;.45= *8 * *8 1'7f 3 "* ' * . * ( 2! *- .5 g! 1g 3 2. ( h ( h8 2" 3 .* ' * . * ( 27h.1=0 speaker $ *7@ 7 3 * 8 '' *;. 4 5 = *8 * *8 1'7f 2! *- .5 g! 1g 3 2. ( h ( h8 *- 2" 3 " * *' *8 i 3 . * *' *8 i 27h.1=1 buzzer
HTG2150 26 july 24, 2000 preliminary mask option the following shows many kinds of mask options in the HTG2150. all the mask options must be de - fined on order to ensure proper system functioning. no. mask option 1 wdt enable/disable selection. wdt can be enabled or disabled by mask option. 2 wake-up selection. this option defines the wake-up activity. external i/o pins (pa only) all have the capability to wake-up the chip from a halt mode by a following edge. 3 external interrupt input pin share with other function selection. int /seg37: int can be set as an external interrupt input pin or lcd segment output pin. 4 i/o pins share with other function selection. pb4/seg33, pb5/seg34, pb6/seg35, pb7/seg36: pb4, pb5, pb6, pb7 can be set as i/o pins or lcd segment output pins. 5 segment output pins share with other function selection. xin/seg39, xout/seg38: seg38, seg39 ban be set as lcd segment output pins or xin, xout pins be connected to a 32768hz crystal. 6 lcd bias register selection. this option describes the lcd bias current. there are three types of selection. * selectable as small, middle or large current. note: *
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instruction set summary mnemonic description instruction cycle flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to register with carry subtract immediate data from acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry with result in data memory decimal adjust acc for addition with result in data memory 1 1 (1) 1 1 1 (1) 1 1 1 (1) 1 1 (1) 1 (1) z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov z,c,ac,ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] and data memory to acc or data memory to acc exclusive-or data memory to acc and acc to data memory or acc to data memory exclusive-or acc to data memory and immediate data to acc or immediate data to acc exclusive-or immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 (1) 1 (1) 1 (1) 1 1 1 1 (1) 1 z z z z z z z z z z z increment and decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 (1) 1 1 (1) z z z z HTG2150 28 july 24, 2000 preliminary
mnemonic description instruction cycle flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 (1) 1 1 (1) 1 1 (1) 1 1 (1) none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 (1) 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 (1) 1 (1) none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditional skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 (2) 1 (2) 1 (2) 1 (2) 1 (3) 1 (3) 1 (2) 1 (2) 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read rom code (current page) to data memory and tblh read rom code (last page) to data memory and tblh 2 (1) 2 (1) none none HTG2150 29 july 24, 2000 preliminary
mnemonic description instruction cycle flag affected miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 (1) 1 (1) 1 1 1 1 (1) 1 1 none none none to,pd to*,pd* to*,pd* none none to,pd note: x: 8 bits immediate data m: 8 bits data memory address a: accumulator i: 0~7 number of bits addr: 13 bits program memory address : flag is affected : flag is not affected * : flag may be affected by the execution status (1) : if a loading to the pcl register occurs, the execution cycle of instructions will be delayed one for one more cycles (4 system clocks) (2) : if a skip to the next instruction occurs, the execution cycle of instructions will be delayed one more cycle (4 system clocks). otherwise the original instruction cycle(s) is unchanged. (3) : (1) or (2) HTG2150 30 july 24, 2000 preliminary
instruction definition adc a,[m] add data memory and carry to accumulator description the contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator. operation acc acc+[m]+c affected flag(s) tc2 tc1 to pd ov z ac c adcm a,[m] add accumulator and carry to data memory description the contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory. operation [m] acc+[m]+c affected flag(s) tc2 tc1 to pd ov z ac c add a,[m] add data memory to accumulator description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc+[m] affected flag(s) tc2 tc1 to pd ov z ac c add a,x add immediate data to accumulator description the contents of the accumulator and the specified data are added, leaving the result in the accumulator. operation acc acc+x affected flag(s) tc2 tc1 to pd ov z ac c HTG2150 31 july 24, 2000 preliminary
addm a,[m] add accumulator to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the data memory. operation [m] acc+[m] affected flag(s) tc2 tc1 to pd ov z ac c and a,[m] logical and accumulator with data memory description data in the accumulator and the specified data memory performs a bitwise logical_and operation. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) tc2 tc1 to pd ov z ac c and a,x logical and immediate data to accumulator description data in the accumulator and the specified data performs a bitwise logi - cal_and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) tc2 tc1 to pd ov z ac c andm a,[m] logical and data memory with accumulator description data in the specified data memory and the accumulator performs a bitwise logical_and operation. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) tc2 tc1 to pd ov z ac c HTG2150 32 july 24, 2000 preliminary
call addr subroutine call description the instruction unconditionally calls a subroutine located at the indicated address. the program counter increments once to obtain the address of the next instruction, and pushes this onto the stack. the indicated address is then loaded. program execution continues with the instruction at this ad - dress. operation stack pc+1 pc addr affected flag(s) tc2 tc1 to pd ov z ac c clr [m] clear data memory description the contents of the specified data memory are cleared to zero. operation [m] 00h affected flag(s) tc2 tc1 to pd ov z ac c clr [m].i clear bit of data memory description the bit i of the specified data memory is cleared to zero. operation [m].i 0 affected flag(s) tc2 tc1 to pd ov z ac c clr wdt clear watchdog timer description the wdt and the wdt prescaler are cleared (re-counting from zero). the power down bit (pd) and time-out bit (to) are cleared. operation wdt and wdt prescaler 00h pd and to 0 affected flag(s) tc2 tc1 to pd ov z ac c 00 HTG2150 33 july 24, 2000 preliminary
clr wdt1 preclear watchdog timer description the pd, to flags, wdt and the wdt prescaler are cleared (re-counting from zero), if the other preclear wdt instruction had been executed. execu - tion of this instruction without the other preclear instruction only sets the indicating flag which implies that this instruction was executed and the pd and to flags remain unchanged. operation wdt and wdt prescaler 00h* pd and to 0* affected flag(s) tc2 tc1 to pd ov z ac c 0* 0* clr wdt2 preclear watchdog timer description the pd, to flags, wdt and the wdt prescaler are cleared (re-counting from zero), if the other preclear wdt instruction had been executed. execu - tion of this instruction without the other preclear instruction, only sets the indicating flag which implies that this instruction was executed and the pd and to flags remain unchanged. operation wdt and wdt prescaler 00h* pd and to 0* affected flag(s) tc2 tc1 to pd ov z ac c 0* 0* cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1
s comple- ment). bits which previously contain a one are changed to zero and vice-versa. operation [m] [m ] affected flag(s) tc2 tc1 to pd ov z ac c HTG2150 34 july 24, 2000 preliminary
cpla [m] complement data memory and place result in accumulator description each bit of the specified data memory is logically complemented (1
s comple - ment). bits which previously contained a one are changed to zero and vice-versa. the complemented result is stored in the accumulator and the contents of the data memory remains unchanged. operation acc [m ] affected flag(s) tc2 tc1 to pd ov z ac c daa [m] decimal-adjust accumulator for addition description the accumulator value is adjusted to the bcd (binary code decimal) code. the accumulator is divided into two nibbles. each nibble is adjusted to the bcd code and an internal carry (ac1) will be done if the low nibble of the ac - cumulator is greater than 9. the bcd adjustment is done by adding 6 to the original value if the original value is greater than 9 or a carry (ac or c) is set; otherwise the original value remains unchanged. the result is stored in the data memory and only the carry flag (c) may be affected. operation if (acc.3~acc.0) >9 or ac=1 then ([m].3~[m].0) (acc.3~acc.0)+6, ac1=ac else ([m].3~[m].0) (acc.3~acc.0), ac1=0 and if (acc.7~acc.4)+ac1 >9 or c=1 then ([m].7~[m].4) (acc.7~acc.4)+6+ac1, c=1 else ([m].7~[m].4) (acc.7~acc.4)+ac1, c=c affected flag(s) tc2 tc1 to pd ov z ac c dec [m] decrement data memory description data in the specified data memory is decremented by one. operation [m] [m] 1 affected flag(s) tc2 tc1 to pd ov z ac c HTG2150 35 july 24, 2000 preliminary
deca [m] decrement data memory and place result in accumulator description data in the specified data memory is decremented by one, leaving the result in the accumulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) tc2 tc1 to pd ov z ac c halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the ram and registers are retained. the wdt and prescaler are cleared. the power down bit (pd) is set and the wdt time-out bit (to) is cleared. operation pc pc+1 pd 1 to 0 affected flag(s) tc2 tc1 to pd ov z ac c 01 inc [m] increment data memory description data in the specified data memory is incremented by one. operation [m] [m]+1 affected flag(s) tc2 tc1 to pd ov z ac c inca [m] increment data memory and place result in accumulator description data in the specified data memory is incremented by one, leaving the result in the accumulator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) tc2 tc1 to pd ov z ac c HTG2150 36 july 24, 2000 preliminary
jmp addr direct jump description bits 0~12 of the program counter are replaced with the directly-specified ad - dress unconditionally, and control is passed to this destination. operation pc addr affected flag(s) tc2 tc1 to pd ov z ac c mov a,[m] move data memory to accumulator description the contents of the specified data memory is copied to the accumulator. operation acc [m] affected flag(s) tc2 tc1 to pd ov z ac c mov a,x move immediate data to accumulator description the 8-bit data specified by the code is loaded into the accumulator. operation acc x affected flag(s) tc2 tc1 to pd ov z ac c mov [m],a move accumulator to data memory description the contents of the accumulator is copied to the specified data memory (one of the data memory). operation [m] acc affected flag(s) tc2 tc1 to pd ov z ac c HTG2150 37 july 24, 2000 preliminary
nop no operation description no operation is performed. execution continues with the next instruction. operation pc pc+1 affected flag(s) tc2 tc1 to pd ov z ac c or a,[m] logical or accumulator with data memory description data in the accumulator and the specified data memory (one of the data memories) performs a bitwise logical_or operation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) tc2 tc1 to pd ov z ac c or a,x logical or immediate data to accumulator description data in the accumulator and the specified data performs a bitwise logi - cal_or operation. the result is stored in the accumulator. operation acc acc or x affected flag(s) tc2 tc1 to pd ov z ac c orm a,[m] logical or data memory with accumulator description data in the data memory (one of the data memories) and the accumulator performs a bitwise logical_or operation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) tc2 tc1 to pd ov z ac c HTG2150 38 july 24, 2000 preliminary
ret return from subroutine description theprogramcounterisrestoredfromthestack.thisisatwo-cycleinstruction. operation pc stack affected flag(s) tc2 tc1 to pd ov z ac c ret a,x return and place immediate data in accumulator description the program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data. operation pc stack acc x affected flag(s) tc2 tc1 to pd ov z ac c reti return from interrupt description the program counter is restored from the stack, and interrupts are enabled by setting the emi bit. emi is the enable master (global) interrupt bit (bit 0; register intc). operation pc stack emi 1 affected flag(s) tc2 tc1 to pd ov z ac c rl [m] rotate data memory left description the contents of the specified data memory is rotated one bit left, with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0-6) [m].0 [m].7 affected flag(s) tc2 tc1 to pd ov z ac c HTG2150 39 july 24, 2000 preliminary
rla [m] rotate data memory left and place result in accumulator description data in the specified data memory is rotated one bit left, with bit 7 rotated into bit 0, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0-6) acc.0 [m].7 affected flag(s) tc2 tc1 to pd ov z ac c rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are together ro - tated one bit left. bit 7 replaces the carry bit; the original carry flag is ro - tated into the bit 0 position. operation [m].(i+1) [m].i; [m].i:bit i of the data memory (i=0-6) [m].0 c c [m].7 affected flag(s) tc2 tc1 to pd ov z ac c rlca [m] rotate left through carry and place result in accumulator description data in the specified data memory and the carry flag are together rotated one bit left. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0 position. the rotated result is stored in the accumulator but the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; [m].i:bit i of the data memory (i=0-6) acc.0 c c [m].7 affected flag(s) tc2 tc1 to pd ov z ac c HTG2150 40 july 24, 2000 preliminary
rr [m] rotate data memory right description the contents of the specified data memory are rotated one bit right with bit 0 rotated to bit 7. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0-6) [m].7 [m].0 affected flag(s) tc2 tc1 to pd ov z ac c rra [m] rotate right and place result in accumulator description data in the specified data memory is rotated one bit right with bit 0 rotated into bit 7, leaving the rotated result in the accumulator. the contents of the data memory remain unchanged. operation acc.(i) [m].(i+1); [m].i:bit i of the data memory (i=0-6) acc.7 [m].0 affected flag(s) tc2 tc1 to pd ov z ac c rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are together ro - tated one bit right. bit 0 replaces the carry bit; the original carry flag is ro- tated into the bit 7 position. operation [m].i [m].(i+1); [m].i:bit i of the data memory (i=0-6) [m].7 c c [m].0 affected flag(s) tc2 tc1 to pd ov z ac c HTG2150 41 july 24, 2000 preliminary
rrca [m] rotate right through carry and place result in accumulator description data of the specified data memory and the carry flag are together rotated one bit right. bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. the rotated result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.i [m].(i+1); [m].i:bit i of the data memory (i=0-6) acc.7 c c [m].0 affected flag(s) tc2 tc1 to pd ov z ac c sbc a,[m] subtract data memory and carry from accumulator description the contents of the specified data memory and the complement of the carry flag are together subtracted from the accumulator, leaving the result in the accumulator. operation acc acc+[m ]+c affected flag(s) tc2 tc1 to pd ov z ac c sbcm a,[m] subtract data memory and carry from accumulator description the contents of the specified data memory and the complement of the carry flag are together subtracted from the accumulator, leaving the result in the data memory. operation [m] acc+[m ]+c affected flag(s) tc2 tc1 to pd ov z ac c HTG2150 42 july 24, 2000 preliminary
sdz [m] skip if decrement data memory is zero description the contents of the specified data memory are decremented by one. if the re - sult is zero, the next instruction is skipped. if the result is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction. this makes a two-cycle instruction. otherwise proceed with the next instruction. operation skip if ([m] 1)=0, [m] ([m] 1) affected flag(s) tc2 tc1 to pd ov z ac c sdza [m] decrement data memory and place result in acc, skip if zero description the contents of the specified data memory are decremented by one. if the re - sult is zero, the next instruction is skipped. the result is stored in the accu - mulator but the data memory remains unchanged. if the result is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction, that makes a two-cycle instruction. otherwise proceed with the next instruction. operation skip if ([m] 1)=0, acc ([m] 1) affected flag(s) tc2 tc1 to pd ov z ac c set [m] set data memory description each bit of the specified data memory is set to one. operation [m] ffh affected flag(s) tc2 tc1 to pd ov z ac c HTG2150 43 july 24, 2000 preliminary
set [m].i set bit of data memory description bit i of the specified data memory is set to one. operation [m].i 1 affected flag(s) tc2 tc1 to pd ov z ac c siz [m] skip if increment data memory is zero description the contents of the specified data memory is incremented by one. if the re - sult is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper in - struction. this is a two-cycle instruction. otherwise proceed with the next instruction. operation skip if ([m]+1)=0, [m] ([m]+1) affected flag(s) tc2 tc1 to pd ov z ac c siza [m] increment data memory and place result in acc, skip if zero description the contents of the specified data memory is incremented by one. if the re - sult is zero, the next instruction is skipped and the result is stored in the ac - cumulator. the data memory remains unchanged. if the result is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction. this is a two-cycle instruction. otherwise proceed with the next instruction. operation skip if ([m]+1)=0, acc ([m]+1) affected flag(s) tc2 tc1 to pd ov z ac c HTG2150 44 july 24, 2000 preliminary
snz [m].i skip if bit i of the data memory is not zero description if bit i of the specified data memory is not zero, the next instruction is skipped. if bit i of the data memory is not zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction. this is a two-cycle instruction. otherwise proceed with the next instruction. operation skip if [m].i 0 affected flag(s) tc2 tc1 to pd ov z ac c sub a,[m] subtract data memory from accumulator description the specified data memory is subtracted from the contents of the accumula - tor, leaving the result in the accumulator. operation acc acc+[m ]+1 affected flag(s) tc2 tc1 to pd ov z ac c subm a,[m] subtract data memory from accumulator description the specified data memory is subtracted from the contents of the accumula - tor, leaving the result in the data memory. operation [m] acc [m ]+1 affected flag(s) tc2 tc1 to pd ov z ac c sub a,x subtract immediate data from accumulator description the immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator. operation acc acc+x +1 affected flag(s) tc2 tc1 to pd ov z ac c HTG2150 45 july 24, 2000 preliminary
swap [m] swap nibbles within the data memory description the low-order and high-order nibbles of the specified data memory (one of the data memories) are interchanged. operation [m].3~[m].0 [m].7~[m].4 affected flag(s) tc2 tc1 to pd ov z ac c swapa [m] swap data memory and place result in accumulator description the low-order and high-order nibbles of the specified data memory are inter - changed, writing the result to the accumulator. the contents of the data memory remain unchanged. operation acc.3~acc.0 [m].7~[m].4 acc.7~acc.4 [m].3~[m].0 affected flag(s) tc2 tc1 to pd ov z ac c sz [m] skip if data memory is zero description if the contents of the specified data memory is zero, the following instruc - tion, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction. this is a two-cycle in- struction. otherwise proceed with the next instruction. operation skip if [m]=0 affected flag(s) tc2 tc1 to pd ov z ac c HTG2150 46 july 24, 2000 preliminary
sza [m] move data memory to acc, skip if zero description the contents of the specified data memory is copied to the accumulator. if the contents is zero, the following instruction, fetched during the current in - struction execution, is discarded and a dummy cycle is replaced to get the proper instruction. this is a two-cycle instruction. otherwise proceed with the next instruction. operation skip if [m]=0 affected flag(s) tc2 tc1 to pd ov z ac c sz [m].i skip if bit i of the data memory is zero description if bit i of the specified data memory is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction. this is a two-cycle instruction. other - wise proceed with the next instruction. operation skip if [m].i=0 affected flag(s) tc2 tc1 to pd ov z ac c tabrdc [m] move rom code (current page) to tblh and data memory description the rom code low byte (current page) addressed by the table pointer (tblp), (tbhp) is moved to the specified data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) tc2 tc1 to pd ov z ac c HTG2150 47 july 24, 2000 preliminary
tabrdl [m] move the rom code (last page) to tblh and data memory description the rom code low byte (last page) addressed by the table pointer (tblp) is moved to the data memory and the high byte transferred to tblh directly. operation [m] rom code (low byte) tblh rom code (high byte) affected flag(s) tc2 tc1 to pd ov z ac c xor a,[m] logical xor accumulator with data memory description data in the accumulator and the indicated data memory performs a bitwise logical exclusive_or operation and the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) tc2 tc1 to pd ov z ac c xorm a,[m] logical xor data memory with accumulator description data in the indicated data memory and the accumulator perform a bitwise logical exclusive_or operation. the result is stored in the data memory. the zero flag is affected. operation [m] acc xor [m] affected flag(s) tc2 tc1 to pd ov z ac c xor a,x logical xor immediate data to accumulator description data in the the accumulator and the specified data perform a bitwise logical exclusive_or operation. the result is stored in the accumulator. the zero flag is affected. operation acc acc xor x affected flag(s) tc2 tc1 to pd ov z ac c HTG2150 48 july 24, 2000 preliminary
HTG2150 49 july 24, 2000 preliminary copyright 2000 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek assumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may pres - ent a risk to human life due to malfunction or otherwise. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3 creation rd. ii, science-based industrial park, hsinchu, taiwan, r.o.c. tel: 886-3-563-1999 fax: 886-3-563-1189 holtek semiconductor inc. (taipei office) 5f, no.576, sec.7 chung hsiao e. rd., taipei, taiwan, r.o.c. tel: 886-2-2782-9635 fax: 886-2-2782-9636 fax: 886-2-2782-7128 (international sales hotline) holtek semiconductor (hong kong) ltd. rm.711, tower 2, cheung sha wan plaza, 833 cheung sha wan rd., kowloon, hong kong tel: 852-2-745-8288 fax: 852-2-742-8657

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